eInfochips Inc · US
Join eInfochips as a Senior Design Verification Engineer and contribute to the development of cutting-edge products. With over two decades of experience in product engineering and semiconductor design services, we are a leading global provider of innovative solutions.
About the Role
We are seeking an experienced Senior Design Verification Engineer to join our team. As a key member of our verification team, you will be responsible for designing and implementing verification environments using UVM and SystemVerilog.
As a senior engineer, you will have the opportunity to work on complex projects, lead teams, and contribute to the development of new technologies.
About eInfochips
eInfochips is a leading global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, we continue to fuel technological innovations in multiple verticals.
Responsibilities:
Build scalable verification environments using UVM and SystemVerilog
Create detailed verification plans from architectural specifications
Write, run, and debug constrained-random tests and directed tests
Define, measure, and close functional and code coverage metrics
Run gate-level simulations to verify power-up and timing states
Develop scripts to automate regression runs and triage failures