Cadence · USA
Senior Verification Engineer
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
About the Role
We're seeking a Senior Verification Engineer to join our team. As a key member of our verification group, you will be responsible for designing and developing system-level AVIP solutions for emulation/prototyping platforms (Palladium, Protium).
Responsibilities:
Design and develop system-level AVIP solutions for emulation/prototyping platforms (Palladium, Protium)
Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation
Develop end-to-end verification flows including: AVIP integration, testbench and system modeling, bare-metal / driver-level validation
Optimize solutions for performance, scalability, and emulation efficiency
Develop custom test cases, tools, and automation to enable advanced use models (embedded / co-emulation / hybrid flows)
Work closely with cross-functional teams (PE, AE, customers) to debug and resolve system-level issues
Support customer enablement, including bring-up, debug, and solution deployment
What We Are Looking For:
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with at least 3 years’ experience
Strong expertise in high-speed protocols such as: PCIe, CXL, AMBA, UCIe, Ethernet (at least one)
RTL design experience (SystemVerilog / Verilog)
C/C++ development experience for modeling, testbench, or system integration
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